1. Field of the Invention
The present invention relates to an improved structure for Double-diffused MOS-technology (DMOS) devices (such as DMOSFETs, Vertical DMOSFETs or "VDMOSFETs", IGBTs etc.), and to a related manufacturing process.
2. Discussion of the Related Art
A power VDMOSFET is a device including, integrated in the same semiconductor chip, several hundred or even thousands elementary cells representing elementary VDMOSFETs connected in parallel in order to contribute a given fraction to the overall current of the power device.
In its simplest form, each elementary cell includes a first region of a given conductivity type (P type for an N-channel device, N type for a P-channel one) formed inside a lightly doped semiconductor layer of the opposite conductivity type (N type or P type, respectively); the lightly doped layer is formed over a heavily doped semiconductor substrate of the same conductivity type, in the case of VDMOSFETs, or of the opposite conductivity type in the case of IGBTs. The first region includes a heavily doped deep body region surrounded by a more lightly doped body region. An annular source region is formed inside the body and deep body regions.
A manufacturing process for an N-channel VDMOSFET is described in "Power MOSFETs: Power for the 80s", D. Grant and A. Tregida, Solid State Technology, November 1985, which is incorporated herein by reference. The process provides for epitaxially growing a lightly doped N type silicon layer over a heavily doped silicon substrate; performing a field oxidation; forming the heavily doped deep body regions; defining active areas of the device; growing a gate oxide layer over said active areas; depositing and doping a polysilicon layer over the gate oxide layer; defining gate regions by selectively etching the polysilicon layer; forming the body regions and the source regions to define the channel of the VDMOSFET; depositing an oxide layer over the entire surface of the chip; defining contact areas in said oxide layer; forming metal layers on the top and bottom surfaces of the chip; and passivating the top surface of the chip.
More evolved VDMOSFET structures are described in the U.S. Pat. No. 5,382,538 and U.S. Pat. No. 4,774,198, both incorporated herein by reference.
For example, in the U.S. Pat. No. 5,382,538 a structure is described wherein the heavily doped deep body regions are formed inside the more lightly doped body regions, and are self-aligned with the polysilicon gate (and thus with the channel regions). A manufacturing process suitable for obtaining this structure differs from the previously described process in that both the lightly doped body regions and the heavily doped deep body regions are formed in a self-aligned manner with the polysilicon gates, and the lightly doped body regions are formed first.
A major problem of power VDMOSFETs is that the lightly doped epitaxial layer, having a significant resistivity, causes the power device to have a high on-state resistance RDSon (the resistance value between drain and source terminals when the device is in the conductive state). High RDSon values result in significant power dissipation.
Furthermore, it is known that power VDMOSFETs which must withstand high drain-source voltages require highly resistive and thick epitaxial layers, and that the RDSon value increases rapidly with the breakdown voltage BV.
In the U.S. Pat. No. 4,974,059 a high power MOSFET structure is disclosed which is substantially similar to the structure described in the already mentioned U.S. Pat. No. 5,382,538, but in which the regions between the elementary cells have the same conductivity type of the epitaxial layer but lower resistivity reducing the RDSon value of the power MOSFET. All these regions are continuous and shallower than the body regions of the VDMOSFET elementary cells.
In view of the state of the art described, it is an object of the present invention to provide a DMOS device structure which allows a reduction of the on-state resistance without affecting the breakdown voltage value.